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MICRO-POLE™ INTERFACE
General Information The Micro-Pole is supplied standard with two different user selectable interfaces.  The available interface choices are either an 8 bit parallel data input, or a serial three wire data input.  Interface selection is made at power-up and is controlled by the state of the PAR/SER# input (pin 12). Tuneword Calculation The tuneword for the Micro-Pole is calculated in the same fashion as for the Mini-Pole and Maxi-Pole.  This calculation is detailed in the catalog on page 2, and as such is not detailed here. Serial Interface Tying the PAR/SER# input low causes the Micro-Pole to receive data in the serial three wire format described below.  A timing diagram is shown in Figure One. Three lines are used in the serial interface.  These are: SCLK, LOAD and A0/SERDAT.  Communications is initiated by the rising edge of LOAD.  The 8 bit tuneword is clocked into the filter MSB first on the A0 line by the rising edge of SCLK.  Once the tuneword has been clocked in, the falling edge of Load initiates the internal tuning sequence.  NOTE: When using the Micro-Pole in the serial mode, the extra data inputs (A1-A7) should be tied either high or low.
Figure One
Parallel Interface Tying the PAR/SER# input high causes the Micro-Pole to receive data in an 8 bit parallel format.  The 8 bit tuneword is presented on A0 through A7, and is latched into the filter by the falling edge of the LOAD pulse.  Once the tuneword is latched, the internal tuning sequence begins.  A timing diagram is shown in Figure Two.  NOTE: When using the Micro-Pole in the parallel mode, the SCLK input should be tied high.
Figure Two
Other Features The Micro-Pole is provided with the capability of shutting down the internal DC to DC converter in the event that the user wishes to decrease power consumption.  The converter is controlled by the SWENA line.  Tying this line to ground inhibits the operation of the converter, and reduces the operating current of the filter.  The filter will not operate in this mode, but the control logic will remain active.  Returning the SWENA line to a high ( or open ) logic level causes the converter to start, and the filter to tune to its last commanded frequency.  Retuning is not required.  This input has an internal pull up resistor, and should be tied high, or left unconnected if the power down feature is not used.
Package Outline	Pinout and Ratings Pin # REF DES DESCRIPTION MAXIMUM RATING 1 GND Ground   2 A7 Tune Bit 7 (MSB)   3 A6 Tune Bit 6   4 A5 Tune Bit 5   5 A4 Tune Bit 4 Vcc + 0.3 VDC 6 A3 Tune Bit 3   7 A2 Tune Bit 2   8 A1 Tune Bit 1   9 A0/SerDat Tune Bit 0 (LSB) or Serial Data   10 Load Interface Control   11 SCLK Serial Clock ­ Vcc + 0.3 VDC 12 PAR/SER Parallel/Serial   13 SWENA Switcher Enable   14 Vcc +3 to +5 VDC   15 GND Ground   16 GND Ground   17 RFOUT RF Out 0 dBm 18 GND Ground   19-27 N/C Do Not Connect   28 GND Ground   29 RFIN RF In 0 dBm 30 GND Ground